Analog-to-Digital Converter (ADC)
212 October 8, 2006
Preliminary
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018
This register indicates underflow conditions in the Sample Sequencer FIFOs. The corresponding
underflow condition can be cleared by writing a 1 to the relevant bit position.
Bit/Field Name Type Reset Description
31:4 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
3 UV3 R/W1C 0 This bit specifies that the FIFO for Sample Sequencer 3 has
hit an und er fl ow con dit ion wh er e the FI FO is empt y and a
read w as requ est ed . Th e probl ema ti c re ad does no t move
the FIFO pointers, and 0s are returned. This bit is cleared by
writing a 1.
2 UV2 R/W1C 0 This bit specifies that the FIFO for Sample Sequencer 2 has
hit an underflow condition where the FIFO is empty and a
read was req uested . Th e probl emati c read does not m ove th e
FIFO pointers, and 0s are returned. This bit is cleared by
writing a 1.
1 UV1 R/W1C 0 This bit specifies that the FIFO for Sample Sequencer 1 has
hit an underflow condition where the FIFO is empty and a
read was req uested . Th e probl emati c read does not m ove th e
FIFO pointers, and 0s are returned. This bit is cleared by
writing a 1.
0 UV0 R/W1C 0 This bit specifies that the FIFO for Sample Sequencer 0 has
hit an underflow condition where the FIFO is empty and a
read was req uested . Th e probl emati c read does not m ove th e
FIFO pointers, and 0s are returned. This bit is cleared by
writing a 1.
reserved UV0
RO
0
ADC Underflow Status (ADCUSTAT)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
UV1
UV2UV3
reserved