LM3S610 Data Sheet
October 8, 2006 209
Preliminary
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C
This register provides the mechanism for clearing interrupt conditions, and shows the status of
controller interrupts generated by the Sample Sequencers. When read, each bit field is the logical
AND of the respective INR and MASK bits. Interrupts are cleared by writing a 1 to the
corresponding bit position. If software is polling the ADCRIS instead of generating interrupts, the
INR bits are still cleared via the ADCISC register, even if the IN bit is not set.
Bit/Field Name T ype Reset Description
31:4 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
3 IN3 R/W1C 0 This bit is set by hardware when the MASK3 and INR3 bits are
both 1, providing a level-based interrupt to the controller. It is
cleared by writing a 1, and also clears the INR3 bit.
2 IN2 R/W1C 0 This bit is set by hardware when the MASK2 and INR2 bits are
both 1, providing a level based interrupt to the controller. It is
cleared by writing a 1, and also clears the INR2 bit.
1 IN1 R/W1C 0 This bit is set by hardware when the MASK1 and INR1 bits are
both 1, providing a level based interrupt to the controller. It is
cleared by writing a 1, and also clears the INR1 bit.
0 IN0 R/W1C 0 This bit is set by hardware when the MASK0 and INR0 bits are
both 1, providing a level based interrupt to the controller. It is
cleared by writing a 1, and also clears the INR0 bit.
reserved IN0
RO
0
ADC Interrupt Status and Clear (ADCISC)
Offset 0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
IN1
IN2IN3
reserved
