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LM3S610-IQN50

LM3S610-IQN50首页预览图
型号: LM3S610-IQN50
PDF文件:
  • LM3S610-IQN50 PDF文件
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功能描述: Microcontroller
PDF文件大小: 2341.71 Kbytes
PDF页数: 共396页
制造商: ETC2[List of Unclassifed Manufacturers]
制造商LOGO: ETC2[List of Unclassifed Manufacturers] LOGO
制造商网址:
捡单宝LM3S610-IQN50
PDF页面索引
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120%
Analog-to-Digital Converter (ADC)
208 October 8, 2006
Preliminary
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the Sample Sequencer raw interrupt signals are promoted to
controller interrupts. The raw interrupt signal for each Sample Sequencer can be masked
independently.
Bit/Field Name T ype Reset Description
31:4 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
3 M ASK3 R/W 0 Specifies whether the raw interrupt signal from Sample
Sequencer 3 (ADCRIS register INR3 bit) is promoted to a
control ler interrup t. If set, th e raw interrup t signal is promoted t o
a controller interrupt. Otherwise, it is not.
2 M ASK2 R/W 0 Specifies whether the raw interrupt signal from Sample
Sequencer 2 (ADCRIS register INR2 bit) is promoted to a
control ler interrup t. If set, th e raw interrup t signal is promoted t o
a controller interrupt. Otherwise, it is not.
1 M ASK1 R/W 0 Specifies whether the raw interrupt signal from Sample
Sequencer 1 (ADCRIS register INR0 bit) is promoted to a
control ler interrup t. If set, th e raw interrup t signal is promoted t o
a controller interrupt. Otherwise, it is not.
0 M ASK0 R/W 0 Specifies whether the raw interrupt signal from Sample
Sequencer 0 (ADCRIS register INR0 bit) is promoted to a
control ler interrup t. If set, th e raw interrup t signal is promoted t o
a controller interrupt. Otherwise, it is not.
reserved MASK0
RO
0
ADC Interrupt Mask (ADCIM)
Offset 0x008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
MASK1
MASK2MASK3
reserved
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