LM3S610 Data Sheet
October 8, 2006 207
Preliminary
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each Sample Sequencer. These bits
may be polled by software to look for interrupt conditions without having to generate controller
interrupts.
Bit/Field Name Type Reset Description
31:4 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
3 INR3 RO 0 Set by hardware when a sample with its respective
ADCSSCTL3 IE bit has completed conversion. This bit is
cleared by writing a 1 to the ADCISC IN3 bit.
2 INR2 RO 0 Set by hardware when a sample with its respective
ADCSSCTL2 IE bit has completed conversion. This bit is
cleared by writing a 1 to the ADCISC IN2 bit.
1 INR1 RO 0 Set by hardware when a sample with its respective
ADCSSCTL1 IE bit has completed conversion. This bit is
cleared by writing a 1 to the ADCISC IN1 bit.
0 INR0 RO 0 Set by hardware when a sample with its respective
ADCSSCTL0 IE bit has completed conversion. This bit is
cleared by writing a 1 to the ADCISC IN0 bit.
reserved INR0
RO
0
ADC Raw Interrupt Status (ADCRIS)
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
INR1
INR2INR3
reserved