Analog-to-Digital Converter (ADC)
206 October 8, 2006
Preliminary
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000
This register controls the activation of the Sample Sequencers. Each Sample Sequencer can be
enabled/d is abled ind ependentl y.
Bit/Field Name Type Reset Description
31:4 reserved RO 0 Reserved bits return an indeterminate value, and should never be
changed.
3 ASEN3 R/W 0 Specifies whether Sample Sequencer 3 is enabled. If set, the
sample sequence logic for Sequencer 3 is active. Otherwise, the
Sequencer is inactive.
2 ASEN2 R/W 0 Specifies whether Sample Sequencer 2 is enabled. If set, the
sample sequence logic for Sequencer 2 is active. Otherwise, the
Sequencer is inactive.
1 ASEN1 R/W 0 Specifies whether Sample Sequencer 1 is enabled. If set, the
sample sequence logic for Sequencer 1 is active. Otherwise, the
Sequencer is inactive.
0 ASEN0 R/W 0 Specifies whether Sample Sequencer 0 is enabled. If set, the
sample sequence logic for Sequencer 0 is active. Otherwise, the
Sequencer is inactive.
reserved ASEN0
RO
0
ADC Active Sample Sequencer (ADCACTSS)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
ASEN1
ASEN2ASEN3
reserved