LM3S610 Data Sheet
October 8, 2006 205
Preliminary
11.5 Register Descriptions
The remainder of this section lists and describes the ADC registers, in numerical order by address
offset.
0x08C ADCSSFSTAT2 0x00000100 RO Sample sequence FIFO 2 status 225
0x0A0 ADCSSMUX3 0x00000000 R/W Sample sequence input multiplexer select 3 226
0x064 ADCSSCTL3 0x00000002 R/W Sample sequence control 3 227
0x0A8 ADCSSFIF O3 0x00000000 RO Sample sequence result FIFO 3 227
0x0AC ADCSSFSTAT3 0x00000100 RO Sample sequence FIFO 3 status 227
0x100 ADCTMLB 0x00000000 R/W Test mode loopback 228
Table 11-2. ADC Register Map (Continued)
Offset Name Reset Type Description
See
page