LM3S610 Data Sheet
October 8, 2006 187
Preliminary
Register 8: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
Bit/Field Name Type Reset Description
31:9 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
8 STALL R/W 0 Watchdog Stall Enable
When set to 1, if the Stellaris microcontroller is stopped
with a debugger , th e watchdog timer stop s counti ng. Once
the microcontroller is restarted, the watchdog timer
resumes cou nting.
7:0 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
RO
0
Watchdog Test (WDTTEST)
Offset 0x418
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO R/W RO RO RO RO RO RO RO RO
STALL
reserved
reserved reserved