LM3S610 Data Sheet
October 8, 2006 183
Preliminary
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C
This register is the interrupt clear register. A write of any value to this register clears the W atchdog
interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is
indeterminate.
Bit/Field Name Type Reset Description
31:0 WDTIntClr WO - Watchdog Interrupt Clear
WDTIntClr
WO
-
Watchdog Interrupt Clear (WDTICR)
Offset 0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type
---------------
WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
WO
-
Reset
Type
---------------
WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
WDTIntClr