LM3S610 Data Sheet
October 8, 2006 177
Preliminary
10 Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, a locking register, and user-enabled stalling.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first
time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has
been configured, the lock register can be written to prevent the timer configuration from being
inadvertently altered.
10.1 Block Diagram
Figure 10-1. WDT Module Block Diagram
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
WDTRIS
WDTMIS
WDTLOCK
WDTTEST
WDTLOAD
WDTVALUE
Comparator
32-Bit Do wn
Counter
0x00000000
Interrupt
System Clock
Identification Registers
WDTPCellID0 WDTPer iphID0 WDT PeriphID4
WDTPCellID1 WDTPer iphID1 WDT PeriphID5
WDTPCellID2 WDTPer iphID2 WDT PeriphID6
WDTPCellID3 WDTPer iphID3 WDT PeriphID7
