General-Purpose Timers
170 October 8, 2006
Preliminary
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count
modes.
Bit/Field Name Type Reset Description
31:16 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
15:0 TBMRL R/W 0xFFFF GPTM TimerB Match Registe r Low
When configured for PWM mode, this value along with
GPTMTBILR, determines the duty cycle of the output PWM
signal.
When configured for Edge Count mode, this value along with
GPTMTBILR, determines ho w ma ny e dge ev ent s are counted.
The total number of edge events counted is equal to the value
in GPTMTBILR minus this value.
TBMRL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W
0
Reset
Type
000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
GPTM TimerB Match (GPTMTBMATCHR)
RO
0
Offset 0x034
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved