LM3S610 Data Sheet
October 8, 2006 169
Preliminary
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count
modes.
Bit/Field Name Type Reset Description
31:16 TAMRH R/W 0xFFFF
(32-bit
mode)
0x0000
(16-bit
mode)
GP TM TimerA Match Regi ste r High
When configured for 32-bit Real -Time C lock (RTC) mode via
the GPTMCFG register, this value is compared to the upper
half of GPTMTAR, to determine match events.
In 16-bit mode, this field read s as 0 and d oes not hav e an ef fect
on the state of GPTMTBMATCHR.
15:0 TAMRL R/W 0xFFFF GPTM TimerA Matc h Regi ste r Low
When configured for 32-bit Real -Time C lock (RTC) mode via
the GPTMCFG register, this value is compa red to the lo wer half
of GPTMTAR, to determine match events.
When configured for PWM mode, this value along with
GPTMTAILR, determines the duty cycle of the output PWM
signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted.
The total number of edge events counted is equal to the value
in GPTMTAILR minus this value.
R/W
Offset 0x030
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
Type
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TAMRH
GPTM TimerA Match (GPTMTAMATCHR)
TAMRL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W
1
Reset
Type
111111111111111
1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode.
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0