LM3S610 Data Sheet
October 8, 2006 167
Preliminary
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028
This register is used to load the starting count value into the timer. When GPTM is configured to
one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond
to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
Bit/Field Name Type Reset Description
31:16 TAILRH R/W 0 xFFFF
(32-bit
mode)
0x0000
(16-bit
mode)
GPTM TimerA Interval Load Register High
When configured for 32-bit mode via the GPTMCFG register,
the GPTM TimerB Interval Lo ad (GPTMTBILR) re gister l oads
this value on a write. A read returns the current value of
GPTMTBILR.
In 16-bit mode, this field read s as 0 and d oes not hav e an ef fect
on the state of GPTMTBILR.
15:0 TAILRL R/W 0xFFFF GPTM TimerA Interval Load Register Low
For both 16- and 32-bit modes, writing this field loads the
counter for TimerA. A read returns the current value of
GPTMTAILR.
TAILRL
R/W
1/0
GPTM TimerA Interval Load (GPTMTAILR)
Offset 0x028
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W
1
Reset
Type
111111111111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TAILRH
1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode.