General-Purpose Timers
166 October 8, 2006
Preliminary
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
Bit/Field Name Type Reset Description
31:11 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
10 CBECINT W1C 0 GPTM CaptureB Event Interrupt Clear
0: The interrupt is unaffected.
1: The interrupt is clea red .
9 CBMCINT W1C 0 GPTM CaptureB Match Interrupt Clear
0: The interrupt is unaffected.
1: The interrupt is clea red .
8 TBTOCINT W1C 0 GPTM TimerB Time-Out Interrupt Clear
0: The interrupt is unaffected.
1: The interrupt is clea red .
7:4 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
3 RTCCINT W1C 0 GPTM RTC Interrupt Clear
0: The interrupt is unaffected.
1: The interrupt is clea red .
2 CAECINT W1C 0 GPTM Captu reA Event Interrupt Clear
0: The interrupt is unaffected.
1: The interrupt is clea red .
1 CAMCINT W1C 0 GPTM CaptureA Match Raw Interrupt
This is the CaptureA match interrupt status after masking.
0 TATOCINT W1C 0 GPTM TimerA Time-Out Raw Interrupt
0: The interrupt is unaffected.
1: The interrupt is clea red .
reserved
RO
0
GPTM Interrupt Clear (GPTMICR)
Offset 0x024
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
00000 00 00000000
RO RO RO W1C W1C W1C W1C RO RO RO RO W1C W1C W1C W1C
CBECINT RTCCINT
reserved
CBMCINT TBTOCINT
reserved
CAECINT CAMCINTTATOCINT