LM3S610 Data Sheet
October 8, 2006 165
Preliminary
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
Bit/Field Name Type Reset Description
31:11 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
10 CBEMIS RO 0 GPTM Capt ureB Event Mask ed Int errupt
This is the Capture B even t interrupt status after masking.
9 CBMMI S R O 0 GPTM CaptureB M atch Masked I nterrupt
This is the CaptureB match interrupt status after masking.
8 T BTOMIS RO 0 GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
7:4 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
3 RTCMIS RO 0 GPTM RT C Ma sk ed Inte rrupt
This is the RTC event interrupt status after masking.
2 CAEM IS RO 0 GPTM Capt ureA Event Mask ed Int errupt
This is the Capture A even t interrupt status after masking.
1 CAMMI S R O 0 GPTM CaptureA M atch Masked I nterrupt
This is the CaptureA match interrupt status after masking.
0 TATOMIS RO 0 GPTM TimerA Time-Out Ma sked Interrupt
This is the TimerA time-out interrupt status after masking.
reserved
RO
0
GPTM Masked Interrupt Status (GPTMMIS)
Offset 0x020
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
CBEMIS
reserved
CBMMIS TBTOMIS
reserved
RTCMIS CAEMIS CAMMIS TATOMIS
