General-Purpose Timers
164 October 8, 2006
Preliminary
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR r egister. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
Bit/Field Name Type Reset Description
31:11 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
10 CBERIS RO 0 GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
9 CBMRIS RO 0 GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
8 TBTORIS RO 0 GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
7:4 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
3 RTCRIS RO 0 GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
2 CAERIS RO 0 GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
1 CAMRIS RO 0 GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
0 TATORIS RO 0 GPTM TimerA Ti me-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
reserved
RO
0
GPTM Raw Interrupt Status (GPTMRIS)
Offset 0x01C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
CBERIS
reserved
CBMRIS TBTORIS
reserved
RTCRIS CAERIS CAMRIS TATORIS
