General-Purpose Timers
162 October 8, 2006
Preliminary
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1
enables the interrupt, while writing a 0 disables it.
Bit/Field Name Type Reset Description
31:11 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
10 CBEIM R/W 0 GPTM CaptureB Event Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
9 CBMIM R/W 0 GPTM CaptureB Match Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
8 TBTOIM R/W 0 GPTM TimerB Time-Out Inte rrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
7:4 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
3 RTCIM R/W 0 GPTM RTC Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
2 CAEIM R/W 0 GPTM CaptureA Event Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
reserved
RO
0
GPTM Interrupt Mask (GPTMIMR)
Offset 0x018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W
CBEIM
reserved
CBMIM
TBTOIM
reserved RTCIM
CAEIM CAMIM TATOIM