LM3S610 Data Sheet
October 8, 2006 151
Preliminary
Figure 9-3. 16-Bit Input Edge Time Mode Example
9.2.3.4 16-Bit PWM Mode
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled
with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TNCMR bit to 0x0, and the TnMR
field to 0x2.
PWM mode can take advantage of the 8-bit prescaler by using the GPTM Timern Prescale
Regist er (GPTMTnPR) and the GPTM Timern Prescale Match Register (GPTMTnPMR). This
effectively extends the range of the timer to 24 bits.
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from
GPTMTnILR (and GPTMTnPR if using a prescaler) and continues counting until disabled by
software clear i ng the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted
in PWM mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTM Timern
Match Register (GPTMnMATCHR). Software has the capability of inverting the output PWM
signal by se tting the TnPWML bit in the GPTMCTL register.
Figure 9-4 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle
assuming a 50-MHz input clock and TnPWML=0 (duty cycle would be 33% for the TnPWML=1
configur at ion ). For this exa mpl e, the start value is GPTMnIRL=0 xC3 50 and the match val ue is
GPTMnMR=0x411A.
GPTMTnR=Y
Input S ig nal
Time
Count
GPTMTnR=X GPTMTnR =Z
Z
X
Y
0xFFFF
