LM3S610 Data Sheet
October 8, 2006 149
Preliminary
9.2.3.2 16-Bit Input Edge Count Mode
In Edge Count mode, the timer is configured as a down-counter capable of capturing three types
of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit
of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined
by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match
(GPTMTnMATCHR) register is configured so that the difference between the value in the
GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events th at
must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register , the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event
count matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in
the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then
reloaded using the value in GPTMTnILR, and stopped since the GPTM automatically clears the
TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are
ignored until TnEN is re-enabled by software.
Figure 9-2 shows how input edge count mode works. In this case, the timer start value is set to
GPTMnILR=0x000A and the match value is set to GPTMnMATCHR=0x0006 so that four edge
events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit af te r
the current count matches the value in the GPTMnMR register.
Table 9-1. 16-Bit Timer With Prescaler Configurations
Prescale #Clock (T
C
)
a
Max Time Units
00000000 1 1.3107 m S
00000001 2 2.6214 m S
00000010 3 3.9321 m S
------------ --
11111100 254 332.9229 mS
11111110 255 334.2336 mS
11111111 256 335.5443 mS
a. T
C
is the clock period.
