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LM3S610-IQN50

LM3S610-IQN50首页预览图
型号: LM3S610-IQN50
PDF文件:
  • LM3S610-IQN50 PDF文件
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功能描述: Microcontroller
PDF文件大小: 2341.71 Kbytes
PDF页数: 共396页
制造商: ETC2[List of Unclassifed Manufacturers]
制造商LOGO: ETC2[List of Unclassifed Manufacturers] LOGO
制造商网址:
捡单宝LM3S610-IQN50
PDF页面索引
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120%
General-Purpose Timers
146 October 8, 2006
Preliminary
9.1 Block Diagram
Figure 9-1. GPTM Module Block Diagram
9.2 Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two
16-bit load/initialization registers and their associated control functions. The exact functionality of
each GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCF G) register (see
page 157), the GPTM TimerA Mode (GPTMTAMR) register (see page 158), and the GPTM
TimerB Mode (GPTMTBMR) register (see page 159). When in one of the 32-bit modes, the timer
can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its
two 16-bit timers configured in any combination of the 16-bit modes.
9.2.1 GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all
control registers are cleared and in their default states. Counters TimerA and TimerB are initialized
to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 167) and the GPTM TimerB Interval Load (GPTMTBILR)
register (see page 168). The prescale counters are initialized to 0x00: the GPTM TimerA
Prescale (GP T MTAPR) register (see page 171) and the GPTM TimerB Prescale (GPTMTBPR)
registe r (see page 172).
9.2.2 32-Bit Timer Operating Modes
Note: Both the odd- and even-numbered CCP pins are used for 16-bit mode. Only the
even-numbered CCP pins are used for 32-bit mode.
TA C om parator
TB C om parator
GPTMTBR
GPTMAR
Clock / Ed g e
Detect
RTC Divider
Clock / Ed g e
Detect
TimerA
Interrupt
TimerB
Interrupt
System
Clock
0x0000 ( Dow n C ounter Modes )
0x0000 ( Dow n C ounter Modes )
CCP (even)
CCP (od d)
En
En
Ti m erA Co ntrol
GPTMTAPMR
GPTMTAILR
GPTMTAMATCHR
GPTMTAPR
GPTMTAMR
Ti m erB Co ntrol
GPTMTBPMR
GPTMTBILR
GPTMTBMATCHR
GPTMTBPR
GPTMTBMR
Interrupt / Config
GPTMCFG
GPTMRIS
GPTMICR
GPTMMIS
GPTMIMR
GPTMCTL
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