LM3S610 Data Sheet
October 8, 2006 143
Preliminary
Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 re gister s are four 8-bit
wide registers, that can conceptually be treated as one 32-bit register. The register is used as a
standard cross-peripheral identification system.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 CID2 RO 0x05 GPIO PrimeCell ID Regi ste r [23 :16 ]
Provides software a standard cross-peripheral identification
system.
reserved
RO
0
GPIO Primecell Identification 2 (GPIOPCellID2)
Offset 0xFF8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000101
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID2