General-Purpose Input/Outp uts (GPIOs)
128 October 8, 2006
Preliminary
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see
page 132). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R,
GPIODR8R, and GPIOSLR) can be set to achieve the desired rise and fall times. The GPIO acts
as an open drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open
drain output when set to 1.
When using the I
2
C module, the GPIO Alternate Function Select (GPIOAFSEL) re gister bit for
PB2 and PB3 should be set to 1 (see examples in “Initialization and Configuration” on page 111).
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 ODE R/W 0x00 Output Pad Open Drain Enable
0: Open drai n conf igu r ati on is dis ab led .
1: Open drai n conf igu r ati on is ena ble d.
reserved
RO
0
GPIO Open Drain Select (GPIOODR)
Offset 0x50C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
ODE
