LM3S610 Data Sheet
October 8, 2006 127
Preliminary
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the
port to be individually configured without affecting the other pads. When writing the DRV8 bit for a
GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the
GPIODR4R register are automatically cleared by hardware.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 DRV8 R/W 0x00 Output Pad 8-mA Drive Enable
A write of 1 to either
GPIODR2[n] or GPIODR4[n] clears the
corresponding 8-mA enable bit. The change is effective on the
second clock cycle after the write.
reserved
RO
0
GPIO 8-mA Drive Select (GPIODR8R)
Offset 0x508
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
DRV8