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LM3S610-IQN50

LM3S610-IQN50首页预览图
型号: LM3S610-IQN50
PDF文件:
  • LM3S610-IQN50 PDF文件
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功能描述: Microcontroller
PDF文件大小: 2341.71 Kbytes
PDF页数: 共396页
制造商: ETC2[List of Unclassifed Manufacturers]
制造商LOGO: ETC2[List of Unclassifed Manufacturers] LOGO
制造商网址:
捡单宝LM3S610-IQN50
PDF页面索引
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120%
General-Purpose Input/Outp uts (GPIOs)
124 October 8, 2006
Preliminary
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register
selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset,
therefore no GPIO line is set to hardware control by default.
Caution – All GPIO pins are inputs by default (GPIODIR=0 and GPIOAFSEL=0), with the
exception of the five JTAG pins (PB7 and PC[3:0]). The JTAG pins default to their JTAG
functionality (GPIOAFSEL=1). Asserting a Power-On-Reset (POR) or an external reset (RST
)
puts both groups of pins back to their default state.
If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down
resistors, and apply RST
or power-cycle the part.
In addition, it is possible to create a software s equence that prevents the debugger from connecting
to the Stellaris microcontroller. If the program code loaded into flash immediately changes the
JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and
halt the controller before the JTAG pin functionality switches. This m ay lock the debugger out of
the part. This can be avoided with a software routine that restores JTAG functionality based on an
external or software trigger.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 AFSEL R/W see note GPIO Alternate Function Select
0: Software control of corresponding GPIO line (GPIO mode).
1: Hardware control of corresponding GPIO line (alternate
hardware function).
Note: The default reset value for the GPIOAFSEL register is
0x00 for all GPIO pins, with the exception of the five
JTAG pins (
PB7 and PC[3:0]). These five pins
default to JTAG functionality. Because of this, the
default reset value of GPIOAFSEL for GPIO Port B is
0x80 while the default reset value of GPIOAFSEL for
Port C is 0x0F.
reserved
RO
0
GPIO Alternate Function Select (GPIOAFSEL)
Offset 0x420
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9876543210
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
0000000- - - - - - - -
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
AFSEL
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