General-Purpose Input/Outp uts (GPIOs)
112 October 8, 2006
Preliminary
GPIO pads and the control register settings required to achieve them. Table 8-2 shows how a
rising edge interrupt would be configured for pin 2 of a GPIO port.
Table 8-1. GPIO Pad Configuration Examples
Configuration
Register Bit Value
a
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
GPIOAFSEL
GPIODIR
GPIOODR
GPIODEN
GPIOPUR
GPIOPDR
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
Digital Input (GPIO) 0001??XXXX
Digital Output (GPIO) 0101??????
Open Drain Input (GPIO) 0011XXXXXX
Open Drain Output (GPIO) 0111XX????
Open Drain Input/Output (I
2
C)1X11XX????
Digital Input (Timer CCP) 1X01??XXXX
Digital Output (PWM) 1X01??????
Digital Output (Timer PWM) 1X01??????
Digital Input/Output (SSI) 1X01??????
Digital Input/Output (UART) 1X01??????
Table 8-2. GPIO Interrupt Configuration Example
Register
Desired Interrupt
Event Trigger
Pin 2 Bit Va lue
a
a. X=Ignored (don’t care bit)
7 6 5 4 3 2 1 0
GPIOIS 0=edge
1=level
XXXXX0XX
GPIOIBE 0=single edge
1=both edges
XXXXX0XX
GPIOIEV 0=Low level, or
negative edge
1=High level, or
positive edge
XXXXX1XX
GPIOIM 0=masked
1=not masked
00000100
