Internal Memory
106 October 8, 2006
Preliminary
Register 9: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear
the interrupt reporting.
Bit/Field Name Type Reset Description
31:2 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
1 PMISC R/W1C 0 Programmi ng Ma sk ed Inte rrupt Statu s and Clea r
This bit indicates whether an interrupt was sign aled
because a programming cycle completed and was not
masked. This bit is cleared by writing a 1. The PRIS bit in
the FCRIS register (see pa ge 104) is also clea red when the
PMISC bit is cleared.
0 AMISC R/W1C 0 Acces s Mask ed Inte rrupt Status and Clea r
This bit indicates whether an interrupt was sign aled
because an improper access was attempted and was not
masked. This bit is cleared by writing a 1. The ARIS bit in
the FCRIS register is also cleared when the AMISC bit is
cleared.
reserved
RO
0
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Offset 0x014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C
AMISC
reserved
PMISC
