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LM3S610-IQN50

LM3S610-IQN50首页预览图
型号: LM3S610-IQN50
PDF文件:
  • LM3S610-IQN50 PDF文件
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功能描述: Microcontroller
PDF文件大小: 2341.71 Kbytes
PDF页数: 共396页
制造商: ETC2[List of Unclassifed Manufacturers]
制造商LOGO: ETC2[List of Unclassifed Manufacturers] LOGO
制造商网址:
捡单宝LM3S610-IQN50
PDF页面索引
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120%
Internal Memory
102 October 8, 2006
Preliminary
Register 6: Flash Memory Control (FMC), offset 0x008
When this register is written, the flash controller initiates the appropriate access cycle for the
location specified by the Flash Memory Address (FMA) register (see page 100). If the access is
a write access, the data contained in the Flash Memory Data (FMD) register (see page 101) is
written.
This is the final register written and initiates the memory operation. There are four control bits in
the lower byte of this register that, when set, initiate the memory operation. The most used of
these register bits are the ERASE and WRITE bits.
It is a programming error to write multiple control bits and the results of such an operation are
unpredictable.
Bit/Field Name Type Reset Description
31:16 WRKEY WO 0x0 Thi s field cont ains a write key, which is used to minimi ze the
inciden ce of accidental flash writes. The va lue 0xA442 must
be written into this field for a write to occur. Writes to the
FMC register without this WRKEY value are ignored. A
read of this field returns the value 0.
15:4 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
3 COMT R/W 0 Commit (write) of register value to nonvolatile storage. A
write of 0 has no effect on the state of this bit.
If read, the st ate of the previous commit acc ess is prov ided.
If the previous commit access is complete, a 0 is returned;
otherwise, if the commit access is not complete, a 1 is
returned.
This can ta ke up to 50 μs.
2 MERASE R/W 0 Mass erase flash memory
If this bit is set, the flash main memory of the device is all
erased. A write of 0 has no effect on the state of this bit.
If read, the state of the previous mass erase access is
provided. If the previous mass erase access is complete, a
0 is returned; ot herwi se , if the pre vi ous ma ss eras e acc es s
is not complete, a 1 is returned.
This can t a ke up to 250 ms .
reserved
WO
0
Flash Memory Control (FMC)
Offset 0x008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
COMT
WRKEY
MERASE
ERASE
WRITE
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