Lattice Semiconductor ispXPGA Family Data Sheet
59
Switching Test Conditions
Figure 25 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 7.
Figure 25. Output Test Load, LVTTL and LVCMOS Standards
Table 7. Text Fixture Required Components
Test Condition R
1
R
2
C
L
Timing Reference VCCO
LVCMOS I/O, (L -> H, H -> L) 106 106 35pF
LVCMOS 3.3 = V
CCO
/2 LVCMOS 3.3 = 3.0V
LVCMOS 2.5 = V
CCO
/2 LVCMOS 2.5 = 2.3V
LVCMOS 1.8 = V
CCO
/2 LVCMOS 1.8 = 1.65V
Default LVCMOS 1.8 I/O (Z -> H) ∞ 106 35pF 0.9V 1.65V
Default LVCMOS 1.8 I/O (Z -> L) 106 ∞ 35pF 0.9V 1.65V
Default LVCMOS 1.8 I/O (H -> Z) ∞ 106 5pF V
OH
- 0.3 1.65V
Default LVCMOS 1.8 I/O (L -> Z) 106 ∞ 5pF V
OL
+ 0.3 1.65V
Note: Output test conditions for all other interfaces are determined by the respective standards.
V
CCO
R
1
R
2
C
L
*
Device
Output
*C
L
includes test fixture and probe capacitance.
Test
Poin