Lattice Semiconductor ispXPGA Family Data Sheet
57
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Symbol Parameter Conditions Min Max Units
t
PWH
Input clock, high time 80% to 80% 1.2 — ns
t
PWL
Input clock, low time 20% to 20% 1.2 — ns
t
R
, t
F
Input Clock, rise and fall time 20% to 80% — 3.0 ns
t
INSTB
Input clock stability, cycle to cycle (peak) — +/- 250 ps
f
MDIVIN
M Divider input, frequency range 10 320 MHz
f
MDIVOUT
M Divider output, frequency range 10 320 MHz
f
NDIVIN
N Divider input, frequency range 10 320 MHz
f
NDIVOUT
N Divider output, frequency range 10 320 MHz
f
VDIVIN
V Divider input, frequency range 100 400 MHz
f
VDIVOUT
V Divider output, frequency range 10 320 MHz
t
OUTDUTY
output clock, duty cycle 40 60 %
t
JIT(CC)
Output clock, cycle to cycle jitter (peak)
Clean reference
1
10MHz ≤ f
MDIVOUT
≤ 40MHz or
100MHz ≤ f
VDIVIN
≤ 160MHz
— +/- 600 ps
Clean reference
1
40MHz ≤ f
MDIVOUT
≤ 320MHz and
160MHz ≤ f
VDIVIN
≤ 400MHz
— +/- 150 ps
t
JIT(PER)
2
Output clock, period jitter (peak)
Clean reference
1
10MHz ≤ f
MDIVOUT
≤ 40MHz or
100MHz ≤ f
VDIVIN
≤ 160MHz
— +/- 600 ps
Clean reference
1
40MHz ≤ f
MDIVOUT
≤ 320MHz and
160MHz ≤ f
VDIVIN
≤ 400MHz
— +/- 150 ps
t
CLK_OUT_DELAY
Input clock to CLK_OUT delay Internal feedback — 3.0 ns
t
PHASE
Input clock to external feedback delta External feedback — 1.5 ns
t
LOCK
Time to acquire phase lock after input stable — 25 us
t
PLL_DELAY
Delay increment (Lead/Lag) Typical = +/- 250ps +/- 120 +/- 550 ps
t
RANGE
Total output delay range (lead/lag) +/- 0.84 +/- 3.85 ns
t
PLL_RSTW
Minimum reset pulse width 1.8 — ns
t
CLK_IN
3
Global clock input delay — 1.0 ns
t
PLL_SEC_DELAY
Secondary PLL output delay — 1.5 ns
1. This condition assures that the output phase jitter will remain within specifications. Jitter spec is based on optimized M, N and V settings
determined by the ispLEVER software.
2. Accumulated jitter measured over 10,000 waveform samples
3. Internal timing for reference only.
