Lattice Semiconductor ispXPGA Family Data Sheet
54
Lock-in Timing
SYDT Timing
TRAINING SEQUENCE SS MODE DATA TRANSFER
SIN
CAL
SYDT
RXD(0:7)
CDRX_SS LOCK-IN (DE-SKEW) TIMING
DATA (SERIAL)
MIN. 1200 SYNCPAT
MIN. 1100 LS CYCL
E
SYNCPAT
DATA (PARALLEL)
t
SUSYNC
t
HDSYNC
SIN
SYDT
RXD(0:9)
CDR_10B12B LOCK-IN TIMING
DATA (SERIAL)
1024 SYNCPAT
SYNCPAT DATA (PARALLEL)
SI
SYDT
N
RXD(0:9)
CDR_8B10B LOCK-IN TIMING
DATA (SERIAL)
240 Idle Pattern(960 TRCP)
Idle Pattern DATA (PARALLEL)
RECCLK
SYDT
RXD(0:9)
SYDT TIMING FOR CDRX_10B12B
SYNC PATTERN
Data0 Data1
Data2
Parallel Data
Data3 Data4
RECCLK
SYDT
RXD(0:9)
SYDT TIMING FOR CDRX_8B10B
K28.5 D21.4 D21.5 D21.5K28.5 D21.4 D21.5 D21.5
IDLE PATTERN
IDLE PATTERN
D0
D1
D2
Data