Lattice Semiconductor ispXPGA Family Data Sheet
46
ispXPGA 1200B/C & ispXPGA 1200EB/EC PFU Timing Parameters
Over Recommended Operating Conditions
Parameter Description
-5
1
-4 -3
UnitsMin. Max. Min. Max. Min. Max.
Functional Delays
LUTs
t
LUT4
4-Input LUT Delay — 0.41 — 0.44 — 0.51 ns
t
LUT5
5-Input LUT Delay — 0.73 — 0.79 — 0.91 ns
t
LUT6
6-Input LUT Delay — 0.86 — 0.93 — 1.07 ns
Shift Register (LUT)
t
LSR_S
Shift Register Setup Time -0.64 — -0.62 — -0.53 — ns
t
LSR_H
Shift Register Hold Time 0.61 — 0.63 — 0.72 — ns
t
LSR_CO
Shift Register Clock to Output Delay — 0.70 — 0.75 — 0.86 ns
Arithmetic Functions
t
LCTHRUR
MC (Macro Cell) Carry In to MC Carry Out Delay (Ripple) — 0.08 — 0.09 — 0.10 ns
t
LCTHRUL
2
MC Carry In to MC Carry Out Delay (Look Ahead) — 0.05 — 0.05 — 0.06 ns
t
LSTHRU
MC Sum In to MC Sum Out Delay — 0.42 — 0.45 — 0.52 ns
t
LSINCOUT
MC Sum In to MC Carry Out Delay — 0.29 — 0.31 — 0.36 ns
t
LCINSOUTR
MC Carry In to MC Sum Out Delay (Ripple) — 0.36 — 0.39 — 0.45 ns
t
LCINSOUTL
MC Carry In to MC Sum Out Delay (Look Ahead) — 0.26 — 0.28 — 0.32 ns
Feed-thru
t
LFT
PFU Feed-Thru Delay — 0.15 — 0.16 — 0.18 ns
Distributed RAM
t
LRAM_CO
Clock to RAM Output — 1.24 — 1.33 — 1.53 ns
t
LRAMAD_S
Address Setup Time -0.41 — -0.40 — -0.34 — ns
t
LRAMD_S
Data Setup Time 0.21 — 0.22 — 0.25 — ns
t
LRAMWE_S
Write Enable Setup Time 0.45 — 0.46 — 0.53 — ns
t
LRAMAD_H
Address Hold Time 0.58 — 0.60 — 0.69 — ns
t
LRAMD_H
Data Hold Time 0.11 — 0.11 — 0.13 — ns
t
LRAMWE_H
Write Enable Hold Time 0.12 — 0.12 — 0.14 — ns
t
LRAMCPW
Clock Pulse Width (High or Low) 2.91 — 3.00 — 3.45 — ns
t
LRAMADO
Address to Output Delay — 0.86 — 0.93 — 1.07 ns
Register/Latch Delays
Registers
t
L_CO
Register Clock to Output Delay — 0.58 — 0.62 — 0.71 ns
t
L_S
Register Setup Time (Data before Clock) 0.14 — 0.14 — 0.16 — ns
t
L_H
Register Hold Time (Data after Clock) -0.12 — -0.12 — -0.10 — ns
t
LCE_S
Register Clock Enable Setup Time -0.11 — -0.11 — -0.09 — ns
t
LCE_H
Register Clock Enable Hold Time 0.11 — 0.11 — 0.13 — ns
Latches
t
L_GO
Latch Gate to Output Delay — 0.09 — 0.10 — 0.12 ns
t
LL_S
Latch Setup Time 0.14 — 0.14 — 0.16 — ns
t
LL_H
Latch Hold Time -0.12 — -0.12 — -0.10 — ns
t
LLPD
Latch Propagation Delay (Transparent Mode) — 0.09 — 0.10 — 0.12 ns
