Lattice Semiconductor ispXPGA Family Data Sheet
45
ispXPGA 1200B/C & ispXPGA 1200EB/EC External Switching
Characteristics
Over Recommended Operating Conditions
Parameter Description Conditions
-5
1
-4 -3
UnitsMin. Max. Min. Max. Min. Max.
t
CO
Global Clock Input to Out-
put
PIO Output Register
— 6.6 — 7.1 — 8.2 ns
t
S
Global Clock Input Setup
PIO Input Register without input
delay
-2.7 — -2.7 — -2.3 — ns
t
H
Global Clock Input Hold
PIO Input Register without input
delay
4.5 — 4.6 — 5.3 — ns
t
SINDLY
Global Clock Input Setup PIO Input Register with input delay 3.8 — 3.8 — 4.4 — ns
t
HINDLY
Global Clock Input Hold PIO Input Register with input delay 0.0 — 0.0 — 0.0 —
t
COPLL
Global Clock Input to
Output
PIO Output Register using PLL
without delay
— 3.1 — 3.3 — 3.8 ns
t
SPLL
Global Clock Input Setup
PIO Input Register without input
delay using PLL without delay
0.5 — 0.5 — 0.6 — ns
t
HPLL
Global Clock Input Hold
PIO Input Register without input
delay using PLL without delay
0.8 — 0.8 — 1.0 — ns
t
SINDLYPLL
Global Clock Input Setup
PIO Input Register with input delay
using PLL without delay
7.6 — 7.6 — 8.8 — ns
t
HINDLYPLL
Global Clock Input Hold
PIO Input Register with input delay
using PLL without delay
-4.1 — -4.0 — -3.4 — ns
1. Only available for ispXPGA 1200B and ispXPGA 1200EB (2.5V/3.3V) devices. Timing v.0.2