Lattice Semiconductor ispXPGA Family Data Sheet
42
ispXPGA 500B/C & ispXPGA 500EB/EC EBR Timing Parameters
Parameter Description
-5
1
-4 -3
UnitsMin. Max. Min. Max. Min. Max.
Synchronous Write
t
EBSWAD_S
Address Setup Delay 0.59 — 0.61 — 0.70 — ns
t
EBSWAD_H
Address Hold Delay -0.40 — -0.39 — -0.33 — ns
t
EBSWCPW
Clock Pulse Width 3.16 — 3.40 — 3.91 — ns
t
EBSWWE_S
Write Enable Setup Time -0.12 — -0.12 — -0.10 — ns
t
EBSWWE_H
Write Enable Hold Time 0.16 — 0.16 — 0.18 — ns
t
EBSWD_S
Data Setup Time 0.27 — 0.28 — 0.32 — ns
t
EBSWD_H
Data Hold Time -0.27 — -0.26 — -0.22 — ns
Synchronous Read
t
EBSR_CO
Clock to Data Delay — 2.04 — 2.19 — 2.52 ns
t
EBSRAD_S
Address Setup Delay 0.10 — 0.10 — 0.12 — ns
t
EBSRAD_H
Address Hold Delay -0.07 — -0.07 — -0.06 — ns
t
EBSRCPW
Clock Pulse Width 3.16 — 3.40 — 3.91 — ns
t
EBSRCE_S
Clock Enable Setup Time -1.76 — -1.71 — -1.45 — ns
t
EBSRCE_H
Clock Enable Hold Time 1.64 — 1.69 — 1.94 — ns
t
EBSRWE_S
Write Enable Setup Time -0.18 — -0.17 — -0.14 — ns
t
EBSRWE_H
Write Enable Hold Time 0.12 — 0.12 — 0.14 — ns
t
EBSRWEEN
Write Enable to Data Enable Time — 1.02 — 1.05 — 1.21 ns
t
EBSRWEDIS
Write Enable to Data Disable Time — 0.99 — 1.02 — 1.17 ns
t
EBSREN
Output Enable to Data Enable Time — 1.02 — 1.05 — 1.21 ns
t
EBSRDIS
Output Enable to Data Disable Time — 0.83 — 0.86 — 0.99 ns
Asynchronous Read
t
EBARADO
Address to New Valid Data Delay — 2.39 — 2.46 — 2.83 ns
t
EBARAD_H
Address to Previous Valid Data Delay — 2.10 — 2.17 — 2.50 ns
t
EBARWEEN
Write Enable to Data Enable Time — 1.01 — 1.04 — 1.20 ns
t
EBARWEDIS
Write Enable to Data Disable Time — 0.98 — 1.01 — 1.16 ns
t
EBAREN
Output Enable to Data Enable Time — 1.02 — 1.05 — 1.21 ns
t
EBARDIS
Output Enable to Data Disable Time — 0.83 — 0.86 — 0.99 ns
1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices. Timing v.0.3
