Lattice Semiconductor ispXPGA Family Data Sheet
39
ispXPGA 500B/C & ispXPGA 500EB/EC External Switching Characteristics
Over Recommended Operating Conditions
Parameter Description Conditions
-5
1
-4 -3
UnitsMin. Max. Min. Max. Min. Max.
t
CO
Global Clock Input to Out-
put
PIO Output Register
— 6.4 — 6.9 — 7.9 ns
t
S
Global Clock Input Setup
PIO Input Register without input
delay
-2.9 — -2.7 — -2.3 — ns
t
H
Global Clock Input Hold
PIO Input Register without input
delay
3.6 — 3.9 — 4.5 — ns
t
SINDLY
Global Clock Input Setup PIO Input Register with input delay 3.3 — 3.6 — 4.1 — ns
t
HINDLY
Global Clock Input Hold PIO Input Register with input delay 0.0 — 0.0 — 0.0 —
t
COPLL
Global Clock Input to
Output
PIO Output Register using PLL
without delay
— 3.2 — 3.4 — 3.9 ns
t
SPLL
Global Clock Input Setup
PIO Input Register without input
delay using PLL without delay
0.1 — 0.2 — 0.3 — ns
t
HPLL
Global Clock Input Hold
PIO Input Register without input
delay using PLL without delay
0.8 — 0.9 — 1.0 — ns
t
SINDLYPLL
Global Clock Input Setup
PIO Input Register with input delay
using PLL without delay
6.7 — 7.2 — 8.3 — ns
t
HINDLYPLL
Global Clock Input Hold
PIO Input Register with input delay
using PLL without delay
-4.3 — -4.0 — -3.4 — ns
1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices. Timing v.0.3
