Lattice Semiconductor ispXPGA Family Data Sheet
27
Figure 23. LVPECL Driver with Three Resistor Pack
ispXPGA 125B/C & ispXPGA 125EB/EC External Switching Characteristics
Over Recommended Operating Conditions
Parameter Description Conditions
-5
1
-4 -3
UnitsMin. Max. Min. Max. Min. Max.
t
CO
Global Clock Input to
Output
PIO Output Register
— 5.3 — 5.7 — 6.6 ns
t
S
Global Clock Input Setup
PIO Input Register without input
delay
-1.9 — -1.8 — -1.5 — ns
t
H
Global Clock Input Hold
PIO Input Register without input
delay
2.7 — 2.9 — 3.3 — ns
t
SINDLY
Global Clock Input Setup PIO Input Register with input delay 3.1 — 3.3 — 3.8 — ns
t
HINDLY
Global Clock Input Hold PIO Input Register with input delay 0.0 — 0.0 — 0.0 —
t
COPLL
Global Clock Input to
Output
PIO Output Register using PLL
without delay
— 3.6 — 3.9 — 4.5 ns
t
SPLL
Global Clock Input Setup
PIO Input Register without input
delay using PLL without delay
0 — 0.1 — 0.3 — ns
t
HPLL
Global Clock Input Hold
PIO Input Register without input
delay using PLL without delay
0.9 — 1.0 — 1.2 — ns
t
SINDLYPLL
Global Clock Input Setup
PIO Input Register with input delay
using PLL without delay
5.1 — 5.5 — 6.3 — ns
t
HINDLYPLL
Global Clock Input Hold
PIO Input Register with input delay
using PLL without delay
-3.0 — -2.8 — -2.4 — ns
1. Only available for ispXPGA 125B and ispXPGA 125EB (2.5V/3.3V) devices. Timing v.0.3
Zo
Zo
Rs
R
D
A
Rs
to LVPECL
differential
receiver
1/4 of Bourns P/N
CAT 16-PC4F12
ispXPLD Emulated
LVPECL Buffer
R
T
=100
