Lattice Semiconductor ispXPGA Family Data Sheet
25
sysIO DC Electrical Characteristics
Over Recommended Operating Conditions
Standard
V
IL
V
IH
V
OL
Max. (V)
V
OH
Min. (V) I
OL
(mA) I
OH
(mA)Min. (V) Max. (V) Min. (V) Max. (V)
LVCMOS 3.3 -0.3 0.8 2.0 5.5
0.4 V
CCO
- 0.4
20, 16, 12,
8, 5.33, 4
-20, -16,-12,
-8, -5.33, -4
0.2 V
CCO
- 0.2 0.1 -0.1
LVCMOS 2.5 -0.3 0.7 1.7 3.6
0.4 V
CCO
- 0.4
16, 12, 8,
5.33, 4
-16, -12, -8,
-5.33, -4
0.2 V
CCO
- 0.2 0.1 -0.1
LVCMOS 1.8
1
-0.3
0.68
3
1.07
3
3.6
0.4 V
CCO
- 0.4
12, 8
1
, 5.33,
4
-12, -8
1
,
-5.33, -4
0.35V
CC
0.65V
CC
0.2 V
CCO
- 0.2 0.1 -0.1
LVTTL -0.3 0.8 2.0 5.5
0.4 V
CCO
- 0.4 4 -4
0.2 V
CCO
- 0.2 0.1 -0.1
PCI 3.3 -0.3
1.08
3
1.5
3
5.5 0.1 V
CCO
0.9 V
CCO
1.5 -0.5
0.3V
CCO
0.5 V
CCO
AGP-1X -0.3
1.08
3
1.5
3
3.6 0.1 V
CCO
0.9 V
CCO
1.5 -0.5
0.3 V
CCO
0.5 V
CCO
SSTL 3 Class I -0.3 V
REF
- 0.2 V
REF
+ 0.2 3.6 0.7 V
CCO
- 1.1 8 -8
SSTL 3 Class II -0.3 V
REF
- 0.2 V
REF
+ 0.2 3.6 0.5 V
CCO
- 0.9 16 -16
SSTL 2 Class I -0.3 V
REF
- 0.18 V
REF
+ 0.18 3.6 0.54 V
CCO
- 0.62 7.6 -7.6
SSTL 2 Class II -0.3 V
REF
- 0.18 V
REF
+ 0.18 3.6 0.35 V
CCO
- 0.43 15.2 -15.2
CTT 3.3 -0.3 V
REF
- 0.2 V
REF
+ 0.2 3.6 V
REF
- 0.4 V
REF
+ 0.4 8 -8
CTT 2.5 -0.3 V
REF
- 0.2 V
REF
+ 0.2 3.6 V
REF
- 0.4 V
REF
+ 0.4 8 -8
HSTL Class I -0.3 V
REF
- 0.1 V
REF
+ 0.1 3.6 0.4 V
CCO
- 0.4 8 -8
HSTL Class III -0.3 V
REF
- 0.1 V
REF
+ 0.1 3.6 0.4 V
CCO
- 0.4 24 -8
GTL+ -0.3 V
REF
- 0.2 V
REF
+ 0.2 3.6 0.6 N/A 36 N/A
1. Design tool default setting.
2. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of
the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND
connections or between the last GND in a bank and the end of a bank
3. Applicable for ispXPGA B devices.