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LFX500B-5FN900C

LFX500B-5FN900C首页预览图
型号: LFX500B-5FN900C
PDF文件:
  • LFX500B-5FN900C PDF文件
  • LFX500B-5FN900C PDF在线浏览
功能描述: ispXPGA Family
PDF文件大小: 535.52 Kbytes
PDF页数: 共115页
制造商: LATTICE[Lattice Semiconductor]
制造商LOGO: LATTICE[Lattice Semiconductor] LOGO
制造商网址: http://www.latticesemi.com
捡单宝LFX500B-5FN900C
PDF页面索引
120%
Lattice Semiconductor ispXPGA Family Data Sheet
21
Absolute Maximum Ratings
1, 2, 3
1.8V 2.5V/3.3V
Supply Voltage (V
CC
) . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V
PLL Supply Voltage (V
CCP
) . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V
Output Supply Voltage (V
CCO
) . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V
IEEE 1149.1 TAP Supply Voltage (V
CCJ
) . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V
Input Voltage Applied
4, 5
. . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V . . . . . . . . . .-0.5 to 5.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . .-65 to 150°C. . . . . . . . . -65 to 150°C
Junction Temperature (T
J
) with Power Applied . .-55 to 150°C. . . . . . . . . -55 to 150°C
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, following the programming specifications).
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and undershoot of -2V to (V
IH
(MAX) + 2) volts not to exceed 6V is permitted for a duration of <20ns.
5. A maximum of 64 I/Os per device with V
IN
> 3.6V is allowed.
Recommended Operating Conditions
E
2
CMOS Erase Reprogram Specifications
Hot Socketing Characteristics
1, 2, 3, 4
Symbol Parameter Min Max Units
V
CC
Supply Voltage for 1.8V device
1
1.65 1.95 V
Supply Voltage for 2.5V device 2.3 2.7 V
Supply Voltage for 3.3V device 3.0 3.6 V
V
CCP
Supply Voltage for PLL and sysHSI blocks, 1.8V devices
1
1.65 1.95 V
Supply Voltage for PLL and sysHSI blocks, 2.5V devices 2.3 2.7 V
Supply Voltage for PLL and sysHSI blocks, 3.3V devices 3.0 3.6 V
V
CCJ
Supply Voltage for IEEE 1149.1 Test Access Port for LVCMOS 1.8V 1.65 1.95 V
Supply Voltage for IEEE 1149.1 Test Access Port for LVCMOS 2.5V 2.3 2.7 V
Supply Voltage for IEEE 1149.1 Test Access Port for LVCMOS 3.3V 3.0 3.6 V
T
J
(COM) Junction Temperature Commercial Operation 0 85 C
T
J
(IND) Junction Temperature Industrial Operation -40 105 C
1. sysHSI specification is valid for V
CC
and V
CCP
= 1.7V to 1.9V.
Parameter Min Max Units
Erase/Reprogram Cycle
1
1,000 Cycles
1. Valid over commercial temperature range.
Symbol Parameter Condition Min Typ Max Units
I
DK
Input or Tristated I/O Leakage Current 0 V
IN
3.0V +/-50 +/-800 μA
1. Insensitive to sequence of V
CC
and V
CCO
when V
CCO
1.0V. For V
CCO
> 1.0V, V
CC
min must be present. However, assumes monotonic
rise/fall rates for V
CC
and V
CCO
, provided (V
IN
- V
CCO
) 3.6V.
2. LVTTL, LVCMOS only.
3. 0 < V
CC
V
CC
(MAX), 0 < V
CCO
V
CCO
(MAX).
4. I
DK
is additive to I
PU
, I
PD
or I
BH
. Device defaults to pull-up until non-volatile cells are active.
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