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LFX500B-5FN900C

LFX500B-5FN900C首页预览图
型号: LFX500B-5FN900C
PDF文件:
  • LFX500B-5FN900C PDF文件
  • LFX500B-5FN900C PDF在线浏览
功能描述: ispXPGA Family
PDF文件大小: 535.52 Kbytes
PDF页数: 共115页
制造商: LATTICE[Lattice Semiconductor]
制造商LOGO: LATTICE[Lattice Semiconductor] LOGO
制造商网址: http://www.latticesemi.com
捡单宝LFX500B-5FN900C
PDF页面索引
120%
Lattice Semiconductor ispXPGA Family Data Sheet
114
For Further Information
In addition to this data sheet, the following Lattice technical notes may be helpful when designing with the ispXPGA
Family:
ispXPGA sysMEM Memory Design and Usage Guidelines (TN1028)
Lattice sysCLOCK PLL Design and Usage Guidelines (TN1003)
sysIO Usage Guidelines for Lattice Devices (TN1000)
ispXP Configuration Usage Guidelines (TN1026)
sysHSI Usage Guide (TN1020)
“E-Series” Industrial
Part Number Gates Voltage Speed Grade Package Balls
LFX125EB-04FN256I 139K 2.5/3.3 -4 Lead-Free fpBGA 256
LFX125EB-03FN256I 139K 2.5/3.3 -3 Lead-Free fpBGA 256
LFX125EC-03FN256I 139K 1.8 -3 Lead-Free fpBGA 256
LFX200EB-04FN256I 210K 2.5/3.3 -4 Lead-Free fpBGA 256
LFX200EB-03FN256I 210K 2.5/3.3 -3 Lead-Free fpBGA 256
LFX200EC-03FN256I 210K 1.8 -3 Lead-Free fpBGA 256
LFX500EB-04FN900I 476K 2.5/3.3 -4 Lead-Free fpBGA 900
LFX500EB-03FN900I 476K 2.5/3.3 -3 Lead-Free fpBGA 900
LFX500EC-03FN900I 476K 1.8 -3 Lead-Free fpBGA 900
Revision History
Date Version Change Summary
Previous Lattice releases.
September 2003 07 Improved typical Icc data for LFX125B/C and LFX500B/C.
Improved external switching characteristics timing numbers for LFX125B/C.
Improved PIC timing numbers for LFX125B/C.
Improved t
IOINDLY
timing numbers for LFX125B/C.
Improved external switching characteristics timing numbers for LFX500B/C.
Improved PIC timing numbers for LFX500B/C.
Improved t
IOINDLY
timing numbers for LFX500B/C.
Enhanced CDR functionality description.
Logic Signal Connections and Signal Descriptions - removed CDRLOCK, LOSS and EXLOSS
descriptions.
January 2004 07.1 Added lead-free package designators.
June 2004 08.0 Updated CDR specifications and reference notes. Removed Source Synchronous (SS:No CAL)
mode references for the sysHSI blocks.
Revised Figures 16 and 24 for clarification.
Clarification of VCC sysHSI Block for 1.8V devices.
Updated IIL and IIH max specification.
Updated LVTTL and PCI 3.3 to support 5V tolerance.
Updated Global Clock Input Setup time specifications.
Clarification of Serial Out LVDS test condition.
Clarification of REFCLK, SS_CLKIN peak-to-peak period jitter condition.
Added sysHSI Reserved pins and footnote.
Removed industrial ordering part numbers.
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