4-20
Pinout Information
Lattice Semiconductor LatticeECP/EC Family Data Sheet
D14 PR2B 2 C VREF1_2
D13 PR2A 2 T VREF2_2
GND GND2 2
GND GND1 1
GND GND1 1
B13 PT26B 1 C
C13 PT26A 1 T
GND GND1 1
C12 PT25B 1 C
D12 PT25A 1 T
A15 PT24B 1 C
B14 PT24A 1 T
D11 PT23B 1 C
C11 PT23A 1 T
E10 PT22B 1 C
E11 PT22A 1 T TDQS22
A14 PT21B 1 C
GND GND1 1
A13 PT21A 1 T
D10 PT20B 1 C
C10 PT20A 1 T
A12 PT19B 1 C VREF2_1
B12 PT19A 1 T VREF1_1
A11 PT18B 1 C
B11 PT18A 1 T
A10 PT17B 0 C PCLKC0_0
GND GND0 0
B10 PT17A 0 T PCLKT0_0
C9 PT16B 0 C VREF1_0
B9 PT16A 0 T VREF2_0
E9 PT15B 0 C
D9 PT15A 0 T
D8 PT14B 0 C
C8 PT14A 0 T TDQS14
A9 PT13B 0 C
GND GND0 0
A8 PT13A 0 T
B8 PT12B 0 C
B7 PT12A 0 T
D7 PT11B 0 C
C7 PT11A 0 T
A7 PT10B 0 C
A6 PT10A 0 T
E7 PT9B 0 C
LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA (Cont.)
Ball Number Ball Function Bank LVDS Dual Function