4-18
Pinout Information
Lattice Semiconductor LatticeECP/EC Family Data Sheet
P8 PB14A 5 T BDQS14
N8 PB14B 5 C
R9 PB15A 5 T
R10 PB15B 5 C
P9 PB16A 5 T VREF2_5
N9 PB16B 5 C VREF1_5
T10 PB17A 5 T PCLKT5_0
GND GND5 5
T11 PB17B 5 C PCLKC5_0
T12 PB18A 4 T WRITEN
T13 PB18B 4 C CS1N
P10 PB19A 4 T VREF1_4
N10 PB19B 4 C CSN
T14 PB20A 4 T VREF2_4
T15 PB20B 4 C D0/SPID7
M10 PB21A 4 T D2/SPID5
GND GND4 4
M11 PB21B 4 C D1/SPID6
R11 PB22A 4 T BDQS22
P11 PB22B 4 C D3/SPID4
R13 PB23A 4 T
R14 PB23B 4 C D4/SPID3
P12 PB24A 4 T
P13 PB24B 4 C D5/SPID2
N11 PB25A 4 T
GND GND4 4
N12 PB25B 4 C D6/SPID1
R12 PB26A 4
GND GND4 4
GND GND4 4
GND GND3 3
N13 PR27B 3 C VREF2_3
N14 PR27A 3 T VREF1_3
P14 PR26B 3 C
P15 PR26A 3 T
R15 PR25B 3 C
R16 PR25A 3 T
M13 PR24B 3 C
M14 PR24A 3 T RDQS24
P16 PR23B 3 C RLM0_PLLC_FB_A
GND GND3 3
N16 PR23A 3 T RLM0_PLLT_FB_A
N15 PR22B 3 C RLM0_PLLC_IN_A
M15 PR22A 3 T RLM0_PLLT_IN_A
LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA (Cont.)
Ball Number Ball Function Bank LVDS Dual Function