4-17
Pinout Information
Lattice Semiconductor LatticeECP/EC Family Data Sheet
K1 PL20B 6 C LLM0_PLLC_IN_A
L2 PL21A 6 T LLM0_PLLT_FB_A
L1 PL21B 6 C LLM0_PLLC_FB_A
M2 PL22A 6 T
M1 PL22B 6 C
N1 PL23A 6 T
GND GND6 6
N2 PL23B 6 C
M4 PL24A 6 T LDQS24
M3 PL24B 6 C
P1 PL25A 6 T
R1 PL25B 6 C
P2 PL26A 6 T
P3 PL26B 6 C
N3 PL27A 6 T VREF1_6
N4 PL27B 6 C VREF2_6
GND GND6 6
GND GND5 5
P4 PB2A 5 T
N5 PB2B 5 C
P5 PB3A 5 T
P6 PB3B 5 C
R4 PB4A 5 T
R3 PB4B 5 C
T2 PB5A 5 T
T3 PB5B 5 C
R5 PB6A 5 T BDQS6
R6 PB6B 5 C
T4 PB7A 5 T
T5 PB7B 5 C
N6 PB8A 5 T
M6 PB8B 5 C
T6 PB9A 5 T
GND GND5 5
T7 PB9B 5 C
P7 PB10A 5 T
N7 PB10B 5 C
R7 PB11A 5 T
R8 PB11B 5 C
M7 PB12A 5 T
M8 PB12B 5 C
T8 PB13A 5 T
GND GND5 5
T9 PB13B 5 C
LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA (Cont.)
Ball Number Ball Function Bank LVDS Dual Function
