4-3
Pinout Information
Lattice Semiconductor LatticeECP/EC Family Data Sheet
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
PICs Associated
with DQS Strobe PIO Within PIC
DDR Strobe (DQS) and
Data (DQ) Pins
P[Edge] [n-4]
ADQ
BDQ
P[Edge] [n-3]
ADQ
BDQ
P[Edge] [n-2]
ADQ
BDQ
P[Edge] [n-1]
ADQ
BDQ
P[Edge] [n]
A [Edge]DQSn
BDQ
P[Edge] [n+1]
ADQ
BDQ
P[Edge] [n+2]
ADQ
BDQ
P[Edge] [n+3]
ADQ
BDQ
Notes:
1. “n” is a Row/Column PIC number
2. The DDR interface is designed for memories that support one DQS strobe per eight bits of
data. In some packages, all the potential DDR data (DQ) pins may not be available.
3. PIC numbering definitions are provided in the “Signal Names” column of the Signal Descrip-
tions table.