4-2
Pinout Information
Lattice Semiconductor LatticeECP/EC Family Data Sheet
TDI I
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence). Pull-up is enabled during configuration.
TDO O Output pin. Test Data out pin used to shift data out of device using 1149.1.
V
CCJ
—V
CCJ
- The power supply pin for JTAG Test Access Port.
Configuration Pads (used during sysCONFIG)
CFG[2:0] I
Mode pins used to specify configuration modes v alues latched on rising edge
of INITN. During configuration, a pull-up is enabled. These are dedicated
pins.
INITN I/O
Open Drain pin. Indicates the FPGA is ready to be configured. During config-
uration, a pull-up is enabled. It is a dedicated pin.
PROGRAMN I
Initiates configuration sequence when asserted low. This pin always has an
active pull-up. This is a dedicated pin.
DONE I/O
Open Drain pin. Indicates that the configuration sequence is complete, and
the startup sequence is in progress. This is a dedicated pin.
CCLK I/O Configuration Clock for configuring an FPGA in sysCONFIG mode.
BUSY/SISPI I/O Read control command in SPI3 or SPIX mode.
CSN I
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled.
CS1N I
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled.
WRITEN I Write Data on Parallel port (Active low).
D[7:0]/SPID[0:7] I/O sysCONFIG Port Data I/O.
DOUT/CSON O
Output for serial configuration data (rising edge of CCLK) when using
sysCONFIG port.
DI/CSSPIN I
Input for serial configuration data (clocked with CCLK) when using sysCON-
FIG port. During configuration, a pull-up is enabled.
Signal Descriptions (Cont.)
Signal Name I/O Descriptions
