3-22
DC and Switching Characteristics
Lattice Semiconductor LatticeECP/EC Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Parameter Descriptions Conditions Min. Typ. Max. Units
f
IN
Input Clock Frequency (CLKI, CLKFB) 25 — 420 MHz
f
OUT
Output Clock Frequency (CLKOP, CLKOS) 25 — 420 MHz
f
OUT2
K-Divider Output Frequency (CLKOK) 0.195 — 210 MHz
f
VCO
PLL VCO F requency 420 — 840 MHz
f
PFD
Phase Detector Input Frequency 25 — — MHz
AC Characteristics
t
DT
Output Clock Duty Cycle Default duty cycle elected
3
45 50 55 %
t
PH
4
Output Phase Accuracy — — TBD UI
t
OPJIT
1
Output Clock Period Jitter
Fout >= 100MHz — — +/- 125 ps
Fout < 100MHz — — 0.02 UIPP
t
SK
Input Clock to Output Clock skew Divider ratio = integer — — +/- 200 ps
t
W
Output Clock Pulse Width At 90% or 10%
3
1——ns
t
LOCK
2
PLL Lock-in Time — — 150 us
t
PA
Programmable Delay Unit 100 250 400 ps
t
IPJIT
Input Clock Period Jitter — — +/- 200 ps
t
FBKDLY
External Feedback Delay — — 10 ns
t
HI
Input Clock High Time 90% to 90% 0.5 — — ns
t
LO
Input Clock Low Time 10% to 10% 0.5 — — ns
t
RST
RST Pulse Width 10 — — ns
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Using LVDS output buffers.
4. Relative to CLKOP.
Rev F 0.17
