3-15
DC and Switching Characteristics
Lattice Semiconductor LatticeECP/EC Family Data Sheet
LatticeECP/EC Internal Timing Parameters
1
Over Recommended Operating Conditions
Parameter Description
-5 -4 -3
UnitsMin. Max. Min. Max. Min. Max.
PFU/PFF Logic Mode Timing
t
LUT4_PFU
LUT4 delay (A to D inputs to F output) - 0.25 - 0.31 - 0.36 ns
t
LUT6_PFU
LUT6 delay (A to D inputs to OFX output) - 0.55 - 0.66 - 0.77 ns
t
LSR_PFU
Set/Reset to output of PFU - 0.81 - 0.98 - 1.14 ns
t
SUM_PFU
Clock to Mux (M0,M1) input setup time 0.08 - 0.10 - 0.11 - ns
t
HM_PFU
Clock to Mux (M0,M1) input hold time -0.06 - -0.07 - -0.08 - ns
t
SUD_PFU
Clock to D input setup time 0.11 - 0.14 - 0.16 - ns
t
HD_PFU
Clock to D input hold time -0.04 - -0.04 - -0.05 - ns
t
CK2Q_PFU
Clock to Q delay, D-type register configura-
tion
- 0.43 - 0.51 - 0.60
ns
t
LE2Q_PFU
Clock to Q delay latch configuration - 0.54 - 0.65 - 0.76 ns
t
LD2Q_PFU
D to Q throughput delay when latch is
enabled
- 0.50 - 0.60 - 0.69
ns
PFU Memory Mode Timing
t
CORAM_PFU
Clock to Output - 0.43 - 0.51 - 0.60 ns
t
SUDATA_PFU
Data Setup Time -0.25 - -0.30 - -0.34 - ns
t
HDATA_PFU
Data Hold Time -0.06 - -0.07 - -0.08 - ns
t
SUADDR_PFU
Address Setup Time -0.66 - -0.79 - -0.92 - ns
t
HADDR_PFU
Address Hold Time -0.27 - -0.33 - -0.38 - ns
t
SUWREN_PFU
Write/Read Enable Setup Time -0.30 - -0.36 - -0.42 - ns
t
HWREN_PFU
Write/Read Enable Hold Time -0.21 - -0.25 - -0.29 - ns
PIC Timing
PIO Input/Output Buffer Timing
t
IN_PIO
Input Buffer Delay - 0.56 - 0.67 - 0.78 ns
t
OUT_PIO
Output Buffer Delay - 2.07 - 2.49 - 2.90 ns
IOLOGIC Input/Output Timing
t
SUI_PIO
Input Register Setup Time (Data Before
Clock)
- 0.12 - 0.14 - 0.17
ns
t
HI_PIO
Input Register Hold Time (Data after Clock) - -0.09 - -0.11 - -0.13 ns
t
COO_PIO
Output Register Clock to Output Delay - 0.82 - 0.98 - 1.15 ns
t
SUCE_PIO
Input Register Clock Enable Setup Time - -0.02 - -0.02 - -0.03 ns
t
HCE_PIO
Input Register Clock Enable Hold Time - 0.12 - 0.14 - 0.17 ns
t
SULSR_PIO
Set/Reset Setup Time 0.10 - 0.12 - 0.14 - ns
t
HLSR_PIO
Set/Reset Hold Time -0.24 - -0.29 - -0.34 - ns
EBR Timing
t
CO_EBR
Clock to output from Address or Data - 3.82 - 4.58 - 5.34 ns
t
COO_EBR
Clock to output from EBR output Register - 0.74 - 0.88 - 1.03 ns
t
SUDATA_EBR
Setup Data to EBR Memory -0.34 - -0.41 - -0.48 - ns
t
HDATA_EBR
Hold Data to EBR Memory 0.37 - 0.44 - 0.52 - ns
t
SUADDR_EBR
Setup Address to EBR Memory -0.34 - -0.41 - -0.48 - ns
t
HADDR_EBR
Hold Address to EBR Memory 0.37 - 0.45 - 0.52 - ns
t
SUWREN_EBR
Setup Write/Read Enable to PFU Memory -0.22 - -0.26 - -0.30 - ns
