3-14
DC and Switching Characteristics
Lattice Semiconductor LatticeECP/EC Family Data Sheet
LatticeECP/EC External Switching Characteristics
Over Recommended Operating Conditions
Figure 3-6. DDR Timings
Parameter Description Device
-5 -4 -3
UnitsMin. Max. Min. Max. Min. Max.
General I/O Pin Parameters (Using Primary Clock without PLL)
1
t
CO
Clock to Output - PIO Output Register LFEC20 — 5.71 — 6.85 — 7.99 ns
t
SU
Clock to Data Setup - PIO Input Register LFEC20 0.00 — 0.00 — 0.00 — ns
t
H
Clock to Data Hold - PIO Input Register LFEC20 3.41 — 4.09 — 4.77 — ns
t
SU_DEL
Clock to Data Setup - PIO Input Register
with data input delay
LFEC20 3.84 — 4.62 — 5.38 — ns
t
H_DEL
Clock to Data Hold - PIO Input Register
with Input Data Delay
LFEC20 -0.44 — -0.54 — -0.61 — ns
f
MAX_IO
LVDS I/O Buffer Frequency LFEC20 — 420 — 378 — 340 MHz
DDR I/O Pin Parameters
2, 3
t
DVADQ
4
Data Valid After DQS (DDR Read) LFEC20 — 0.192 — 0.192 — 0.192 UI
t
DVEDQ
4
Data Hold After DQS (DDR Read) LFEC20 0.668 — 0.668 — 0.668 — UI
t
DQVBS
Data Valid Before DQS LFEC20 0.2 — 0.2 — 0.2 — UI
t
DQVAS
Data Valid After DQS LFEC20 0.2 — 0.2 — 0.2 — UI
f
MAX_DDR
DDR Clock Frequency LFEC20 95 200 95 166 95 133 MHz
Primary and Secondary Clock
f
MAX_PRI
Frequency for Primary Clock Tree LFEC20 — 420 — 378 — 340 MHz
t
W_PRI
Clock Pulse Width for Primary Clock LFEC20 1.19 — 1.19 — 1.19 — ns
t
SKEW_PRI
Primary Clock Skew within an I/O Bank LFEC20 — 250 — 300 — 350 ps
1. General timing numbers based on LVCMOS2.5V, 12 mA.
2. DDR timing numbers based on SSTL I/O.
3. DDR specifications are characterized but not tested.
4. UI is average bit period.
Rev F 0.17
t
DQVAS
t
DQVBS
DQ and DQS Write Timings
t
DQS
DQ
DQS
DQ
DVEDQ
t
DVADQ
DQ and DQS Read Timings
