3-6
DC and Switching Characteristics
Lattice Semiconductor LatticeECP/EC Family Data Sheet
sysIO Single-Ended DC Electrical Characteristics
Input/Output
Standard
V
IL
V
IH
V
OL
Max.
(V)
V
OH
Min.
(V)
I
OL
1
(mA)
I
OH
1
(mA)Min. (V) Max. (V) Min. (V) Max. (V)
LVCMOS 3.3 -0.3 0.8 2.0 3.6
0.4 V
CCIO
- 0.4
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
0.2 V
CCIO
- 0.2 0.1 -0.1
LVTTL -0.3 0.8 2.0 3.6
0.4 V
CCIO
- 0.4
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
0.2 V
CCIO
- 0.2 0.1 -0.1
LVCMOS 2.5 -0.3 0.7 1.7 3.6
0.4 V
CCIO
- 0.4
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
0.2 V
CCIO
- 0.2 0.1 -0.1
LVCMOS 1.8 -0.3 0.35V
CCIO
0.65V
CCIO
3.6
0.4 V
CCIO
- 0.4 16, 12, 8, 4 -16, -12, -8, -4
0.2 V
CCIO
- 0.2 0.1 -0.1
LVCMOS 1.5 -0.3 0.35V
CCIO
0.65V
CCIO
3.6
0.4 V
CCIO
- 0.4 8, 4 -8, -4
0.2 V
CCIO
- 0.2 0.1 -0.1
LVCMOS 1.2 -0.3 0.35V
CC
0.65V
CC
3.6
0.4 V
CCIO
- 0.4 6, 2 -6, -2
0.2 V
CCIO
- 0.2 0.1 -0.1
PCI -0.3 0.3V
CCIO
0.5V
CCIO
3.6 0.1V
CCIO
0.9V
CCIO
1.5 -0.5
SSTL3 class I -0.3 V
REF
- 0.2 V
REF
+ 0.2 3.6 0.7 V
CCIO
- 1.1 8 -8
SSTL3 class II -0.3 V
REF
- 0.2 V
REF
+ 0.2 3.6 0.5 V
CCIO
- 0.9 16 -16
SSTL2 class I -0.3 V
REF
- 0.18 V
REF
+ 0.18 3.6 0.54 V
CCIO
- 0.62 7.6 -7.6
SSTL2 class II -0.3 V
REF
- 0.18 V
REF
+ 0.18 3.6 0.35 V
CCIO
- 0.43 15.2 -15.2
SSTL18 class I -0.3 V
REF
- 0.125 V
REF
+ 0.125 3.6 0.4 V
CCIO
- 0.4 6.7 -6.7
HSTL15 class I -0.3 V
REF
- 0.1 V
REF
+ 0.1 3.6 0.4 V
CCIO
- 0.4 8 -8
HSTL15 class III -0.3 V
REF
- 0.1 V
REF
+ 0.1 3.6 0.4 V
CCIO
- 0.4 24 -8
HSTL18 class I -0.3 V
REF
- 0.1 V
REF
+ 0.1 3.6 0.4 V
CCIO
- 0.4 9.6 -9.6
HSTL18 class II -0.3 V
REF
- 0.1 V
REF
+ 0.1 3.6 0.4 V
CCIO
- 0.4 16 -16
HSTL18 class III -0.3 V
REF
- 0.1 V
REF
+ 0.1 3.6 0.4 V
CCIO
- 0.4 24 -8
1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as
shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or
between the last GND in a bank and the end of a bank.
Rev F 0.17
