2-33
Architecture
Lattice Semiconductor LatticeECP/EC Family Data Sheet
Oscillator
Ev ery LatticeECP/EC de vice has an internal CMOS oscillator which is used to derive a master serial clock for con-
figuration. The oscillator and the master serial clock run continuously. The def ault value of the master serial clock is
2.5MHz. Table 2-15 lists all the available Master Serial Clock frequencies. When a different Master Ser ial Clock is
selected during the design process, the following sequence takes place:
1. User selects a different Master Serial Clock frequency.
2. During configuration the device starts with the default (2.5MHz) Master Serial Clock frequency.
3. The clock configuration settings are contained in the early configuration bit stream.
4. The Master Serial Clock frequency changes to the selected frequency once the clock configuration bits are
received.
For further inf ormation on the use of this oscillator for configur ation, please see details of additional technical docu-
mentation at the end of this data sheet.
Table 2-15. Selectable Master Serial Clock (CCLK) Frequencies During Configuration
Density Shifting
The LatticeECP/EC family has been designed to ensure that different density devices in the same package have
the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design
targeted for a high-density device to a lower density device. However, the exact details of the final resource utiliza-
tion will impact the likely success in each case.
CCLK (MHz) CCLK (MHz) CCLK (MHz)
2.5* 13 45
4.3 15 51
5.4 20 55
6.9 26 60
8.1 30 130
9.2 34 —
10.0 41 —
