2-31
Architecture
Lattice Semiconductor LatticeECP/EC Family Data Sheet
Table 2-14. Supported Output Standards
Hot Socketing
The LatticeECP/EC devices have been carefully designed to ensure predictable behavior during power-up and
power-down. Power supplies can be sequenced in any order. Dur ing power up and power-down sequences, the
I/Os remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition,
leakage into I/O pins is controlled to within specified limits, this allows for easy integration with the rest of the
system. These capabilities make the LatticeECP/EC ideal for many multiple power supply and hot-swap applica-
tions.
Recommended Power Up Sequence: As descr ibed in the previous paragraph, the supplies can be sequenced
in any order. However, once internal power good is achieved (determined by VCC, VCCAUX, VCCIO bank 5) the
part releases I/Os from tri-state and the management of I/Os becomes the designers responsibility. To simplify a
system design it is therefore recommended that supplies be sequenced VCCIO, VCC, VCCAUX.
Output Standard Drive V
CCIO
(Nom.)
Single-ended Interfaces
LVTTL 4mA, 8mA, 12mA, 16mA, 20mA 3.3
LVCMOS33 4mA, 8mA, 12mA 16mA, 20mA 3.3
LVCMOS25 4mA, 8mA, 12mA, 16mA, 20mA 2.5
LVCMOS18 4mA, 8mA, 12mA, 16mA 1.8
LVCMOS15 4mA, 8mA 1.5
LVCMOS12 2mA, 6mA 1.2
LVCMOS33, Open Drain 4mA, 8mA, 12mA 16mA, 20mA —
LVCMOS25, Open Drain 4mA, 8mA, 12mA 16mA, 20mA —
LVCMOS18, Open Drain 4mA, 8mA, 12mA 16mA —
LVCMOS15, Open Drain 4mA, 8mA —
LVCMOS12, Open Drain 2mA, 6mA —
PCI33 N/A 3.3
HSTL18 Class I, II, III N/A 1.8
HSTL15 Class I, III N/A 1.5
SSTL3 Class I, II N/A 3.3
SSTL2 Class I, II N/A 2.5
SSTL18 Class I N/A 1.8
Differential Interfaces
Differential SSTL3, Class I, II N/A 3.3
Differential SSTL2, Class I, II N/A 2.5
Differential SSTL18, Class I N/A 1.8
Differential HSTL18, Class I, II, III N/A 1.8
Differential HSTL15, Class I, III N/A 1.5
LVDS N/A 2.5
BLVDS
1
N/A 2.5
LVPECL
1
N/A 3.3
RSDS
1
N/A 2.5
1. Emulated with external resistors.