2-30
Architecture
Lattice Semiconductor LatticeECP/EC Family Data Sheet
options for dr ive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain.
Other single-ended standards suppor ted include SSTL and HSTL. Differential standards supported include LVDS,
BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/O standards
(together with their supply and reference voltages) supported by the LatticeECP/EC devices. For further informa-
tion on utilizing the sysIO buffer to support a variety of standards please see the details of additional technical inf or-
mation at the end of this data sheet.
Table 2-13. Supported Input Standards
Input Standard V
REF
(Nom.) V
CCIO
1
(Nom.)
Single Ended Interfaces
LVTTL — —
LVCMOS33
2
——
LVCMOS25
2
——
LVCMOS18 — 1.8
LVCMOS15 — 1.5
LVCMOS12
2
——
PCI — 3.3
HSTL18 Class I, II 0.9 —
HSTL18 Class III 1.08 —
HSTL15 Class I 0.75 —
HSTL15 Class III 0.9 —
SSTL3 Class I, II 1.5 —
SSTL2 Class I, II 1.25 —
SSTL18 Class I 0.9 —
Differential Interfaces
Differential SSTL18 Class I — —
Differential SSTL2 Class I, II — —
Differential SSTL3 Class I, II — —
Differential HSTL15 Class I, III — —
Differential HSTL18 Class I, II, III — —
LVDS, LVPECL, BLVDS, RSDS — —
1. When not specified V
CCIO
can be set anywhere in the valid operating range.
2. JTAG inputs do not have a fixed threshold option and always follow V
CCJ.
