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Introduction
Lattice Semiconductor LatticeECP/EC Family Data Sheet
Introduction
The LatticeECP/EC family of FPGA devices has been optimized to deliver mainstream FPGA features at low cost.
For maximum performance and value , the LatticeECP (EConom y Plus) FPGA concept combines an efficient FPGA
fabr ic with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECP-DSP
(EConomy Plus DSP) family, providing dedicated high-perfor mance DSP blocks on-chip. The LatticeEC™ (ECon-
omy) family suppor ts all the general purpose features of LatticeECP devices without dedicated function blocks to
achieve lower cost solutions.
The LatticeECP/EC FPGA f abric, which was designed from the outset with low cost in mind, contains all the critical
FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mainstream I/Os.
Dedicated DDR memory interf ace logic is also included to support this memory that is becoming increasingly prev-
alent in cost-sensitive applications.
The ispLEVER
®
design tool from Lattice allo ws large complex designs to be efficiently implemented using the Latti-
ceECP/EC family of FPGA devices. Synthesis library support for LatticeECP/EC is available for popular logic syn-
thesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning
tools to place and route the design in the LatticeECP/EC device. The ispLEVER tool extracts the timing from the
routing and back-annotates it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP/EC
family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their
design, increasing their productivity.
